1. Technical Field
The present invention relates generally to data processing; and, more particularly, it relates to data processing that employs reconfigurable logic circuitry.
2. Related Art
Conventional systems that perform data processing do not possess the ability to adapt to various data types on which a data processor must operate. Specific application specific integrated circuitry or other processing circuitry geared and designed to execute specific and limited applications do provide for extremely fast processing, but at a cost of significantly limited functionality. In addition, present signal processors do not provide hardware oriented solutions. For each computational operations within modern signal processors, the signal processor performs multiple functions including a program random access memory (RAM) or a program read only memory (ROM). The conventional signal processor must also employ a data random access memory (RAM) or a plurality of data registers, several address buses and data buses, a data address unit, and a predetermined data path.
Conventional signal processors that employ hardware directed solutions typically provide a limited functionality to a plurality of input data and drive that plurality of input data to a next function. In other words, conventional hardware solutions are geared primarily to perform a very limited number of functions. Limitations of general purpose signal processors employing conventional techniques are numerous; however, a main limitation is an inability to perform a substantially wide variety of operations to accommodate various pluralities of input data. To perform a wide variety of functions, conventional signal processors typically need to perform a large number of gate toggles with each operation.
Further limitations and disadvantages of conventional and traditional systems will become apparent to one of skill in the art through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.
Various aspects of the present invention can be found in a signal processor having a programmable logic circuitry that operates on a plurality of data. The signal processor contains, among other things, a programmable logic configuration circuitry that provides a logic configuration to the programmable logic circuitry. In certain embodiments of the invention, the signal processor employs a wide word width to program the programmable logic circuitry, the wide word width is operable to configure an entirety of the programmable logic circuitry. The programmable logic configuration circuitry further contains a default configuration circuitry and an adaptive configuration circuitry. The default configuration circuitry contains a default logic configuration for the programmable logic circuitry. In other embodiments of the invention, the adaptive configuration circuitry generates an adaptive logic configuration for the programmable logic circuitry. The programmable logic circuitry is partitioned into a plurality of areas. Each area within the plurality of areas is independently programmable with the logic configuration.
In addition, in certain embodiments of the invention, a first logic configuration, provided from an active configuration circuitry, is used to program the programmable logic configuration circuitry while a second logic configuration is simultaneously being loaded into a loading configuration circuitry. In certain embodiments of the invention, the loading configuration circuitry is a memory buffer that receives the other logic configuration while the first logic configuration is used to program the programmable logic configuration circuitry thereby providing extremely fast operation within the signal processor.